IDF2007:Intel's Nehalem to feature eight cores, 16 threads

Then Paul moved onto talk of Intel’s next-gen processor architecture dubbed Nehalem. We’ve given you some details regarding Nehalem in the past as well.  It will be available in the second half of next year and is designed to be a module architecture that can have multiple different cache, core, and I/O configurations.  Nehalem will also feature finer-grained clock gating technology for improved efficiency.


According to the keynote, Nehalem will feature 8-cores on a single die and each core can process two threads, for a total of 16 threads per 8-core CPU.  Nehalem processors will be comprised of roughly 731M transistors and feature a number of new technologies.


At this point, Paul brought out Glenn Hinton to speak of the company’s goals with Nehalem.  Glenn said they planned to build the highest performance core yet that’s scalable to any number of different platforms.  He spoke about the processor’s Quick Path Memory controller and Quick Path Interconnect, which are marketing terms for Nehalem’s integrated memory controller and serial interface.  Then Glenn and Paul showed of a full functional machine running XP on Nehalem and also mentioned that this morning Intel booted OSX on early Nehalem samples.

Nehalem: Single die, 8-cores, 731M transistors, 16 threads, memory controller, graphics, amazing.

[ 本帖最後由 sxs112.tw 於 2007-9-19 10:37 編輯 ]